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      1. 64K Parallel read memory eeprom AT28C64B-20JA
        64K Parallel read memory eeprom AT28C64B-20JA

        64K Parallel read memory eeprom AT28C64B-20JA

        Model NO.
        AT28C64B-20JA
        Price:
        USD 0.10-10.00 / pieces
        Minimum order quantity:
        10 pieces
        Supply Ability:
        100000 pieces / Day
        Country of Origin:
        Shenzhen
        Quantity:
        • Place of Origin:US;33145
        • D/C:2015+
        • Type:LOGIC ICS
        • Brand Name:N/A
        • Package:32-PLCC
        • Model Number:AT28C64B-20JA
        • Package / Case:32-PLCC
        • Operating Temperature:-40°C ~ 125°C
        • Dissipation Power:Standard
        • Application:Computer
        • Supply Voltage:4.5 V ~ 5.5 V

        Data sheet

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        Product Photos32-PLCC
        Standard Package32
        CategoryIntegrated Circuits (ICs)
        FamilyMemory
        Series-
        Format - MemoryEEPROMs - Parallel
        Memory TypeEEPROM
        Memory Size64K (8K x 8)
        Speed200ns
        InterfaceParallel
        Voltage - Supply4.5 V ~ 5.5 V
        Operating Temperature-40°C ~ 125°C
        Package / Case32-LCC (J-Lead)
        Supplier Device Package32-PLCC
        PackagingTube

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        Description

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        The AT28C64B is a high-performance electrically-erasable and programmable readonly
        memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
        Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers
        access times to 150 ns with power dissipation of just 220 mW. When the device is
        deselected, the CMOS standby current is less than 100 μA.


        The AT28C64B is accessed like a Static RAM for the read or write cycle without the
        need for external components. The device contains a 64-byte page register to allow
        writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
        64 bytes of data are internally latched, freeing the address and data bus for other
        operations. Following the initiation of a write cycle, the device will automatically write
        the latched data using an internal control timer. The end of a write cycle can be
        detected by DATA POLLING of I/O7. Once the end of a write cycle has been
        detected, a new access for a read or write can begin.

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